The present invention relates to crystalline originated pits (COP""s) in silicon wafers, and more particularly to the electrical effects of COP""s on semiconductor devices.
Silicon substrates are manufactured with varying amount of crystalline originated pits (COP""s) defects. COP""s are vacancies in the crystalline structure of the substrate. A semiconductor device manufacturer can decide to purchase silicon wafers with a maximum amount of COP""s. Typically, the more COP""s a substrate has, the less expensive it is. The semiconductor device manufacturer can quantify the COP""s in the substrate but has difficulty in determining the electrical effects on the semiconductor devices that would be on the substrate. Thus, it is unknown how large of an effect the COP""s would have on the yield for that substrate. Understanding the effect on yield would help the semiconductor device manufacturer to determine what quality of substrate would be needed to meet a certain specification.
Accordingly, there exists a need for a method for evaluating the effect of COP""s in a silicon substrate on semiconductor devices. The present invention addresses such a need.
A method for evaluating the effect of crystalline originated pits (COP""s) in a silicon substrate on semiconductor devices method locates a first test structure created on a COP on the substrate and a second test structure created on the substrate but not on a COP. The electrical properties of the first and second test structure are then examined and compared. If there is a difference in their electrical properties, then the COP would affect a structure similar to the test structures of a semiconductor device. In this manner, the effects of COP""s on the yield for the substrate can be understood.